1. Field of the Invention
The present invention relates to a semiconductor device, particularly to a semiconductor device having high electrostatic breakdown resistance, and to a method of fabricating the same.
2. Description of Related Art
With the miniatuarization of semiconductor devices, a technique of forming silicide layers on surfaces of impurity-diffusion layers constituting source and drain regions of a MOS transistor is widely used to reduce the parasitic resistance in the impurity-diffusion layer. The switching speed of MOS transistors can be increased by reducing the parasitic resistance in the source and drain regions in this manner, thereby increasing the operation speed.
However, in the case where a MOS transistor is used as a discharge element in the electrostatic protection circuit. built in an input/output circuit of a semiconductor integrated circuit device, reduction of the parasitic resistance in the source and drain regions decreases the electrostatic discharge (ESD) breakdown voltage. The major reason for the decrease in the ESD breakdown voltage is that the reduction of the parasitic resistance in the source and drain regions tends to cause current concentration, giving rise to thermal destruction.
To avoid decrease in the ESD breakdown voltage due to the reduction of the parasitic resistance in the source and drain regions, a technique of partially or completely preventing formation of a silicide layer in the source and drain regions of the MOS transistor as a discharge element has been known (Japanese patent application Laid-open No. 1-259560, No. 2-271673, and No. 2-271674).
However, this technique requires a protection process for partly removing the silicide layer from the source and drain regions of the MOS transistor. When the protection process is carried out in a salicide process for forming a siliside layer, following problems may occur. The problems become obvious for design rules of 0.8 xcexcm or less, particularly of 0.35 xcexcm or less.
Specifically, in the came of forming an oxide film on the entire surface of the wafer after forming the source and drain regions and then removing the oxide film by etching only in the area for forming a silicide layer, a side wall insulation layer which has been formed, is also partially removed. This may cause leakage between a gate electrode and the source/drain regions.
In a full salicide process in which a silicide layer is formed on both the gate electrode and the source/drain regions, it is very difficult in view of limitations to the process to selectively form a silicide layer on a gate electrode while preventing formation of a silicide layer in the vicinity of a drain junction. Specifically, since preventing formation of a silicide layer in the vicinity of the drain junction unavoidably accompanies formation of a mask (or an oxide layer) for preventing formation of a silicide layer on the gate electrode, a silicide layer is not formed on a part of the gate electrode, and the sheet resistance increases to several kilo ohms, for example. Consequently, high speed operations cannot be expected.
An objective of the present invention is to provide a semiconductor device which can be fabricated by utilizing a full salicide technique, can perform high-speed operations, and has a superior ESD breakdown voltage, and a method of fabricating such a semiconductor device.
According to a first aspect of the present invention, there is provided a semiconductor device comprising:
an insulated-gate field-effect transistor which is formed in a first region of a first conductive type and includes a gate insulation layer of a gate electrode, side wall insulation layers formed on side surfaces of the gate electrode, a first impurity-diffusion layer of a second conductive type which is a source region, and a second impurity-diffusion layer of the second conductive type which is a drain region;
a bipolar transistor which includes the second impurity-diffusion layer as a collector region, part of the first region as a base region, and a third impurity-diffusion layer of the second conductive type which is electrically isolated from the second impurity-diffusion layer and is used as an emitter region; and
a Zener diode formed of a fourth impurity-diffusion layer of the second conductive type which is continuously formed with the second impurity-diffusion layer, and a fifth impurity-diffusion layer of the first conductive type which is connected to the fourth impurity-diffusion layer;
wherein silicide layers are formed on the surfaces of the first and second impurity-diffusion layers; and
wherein a protection layer is formed on a surface of the fourth impurity-diffusion layer of the Zener diode.
This semiconductor device has the following effects.
(1) since a silicide layer can be formed in the source and drain regions of the insulated-gate field-effect transistor (hereinafter called AMOS transistor), the MOS transistor can be operated at a high speed without impairing the operation speed. Moreover, since the semiconductor device utilizes a Zener diode as a discharge element of an electrostatic protection circuit, a breakdown voltage between the collector and the base of the bipolar transistor can be decreased by the Zener diode. This ensures the bipolar transistor to be turned on reliably allowing an electrostatic charge to be discharged safely.
(2) Since a silicide layer is not formed on the impurity-diffusion layer constituting the Zener diode due-to the protection layer, changes in the impurity concentration in the impurity-diffusion layer to be caused by the silicide layer can be prevented. As a result, the Zener voltage (junction breakdown voltage) of the Zener diode does not change, thereby preventing malfunction.
(3) The Zener diode is composed of the impurity-diffusion layers differing from the impurity-diffusion layer (drain region) of the MOS transistor. Therefore, the impurity concentrations of the impurity-diffusion layers of the first and second conductive types can be appropriately determined. Consequently, the Zener voltage of the Zener diode can be easily and most suitably controlled.
The protection layer may be formed as follows. Since such protection layer can be formed in the fabrication step of the MOS transistor, the number of fabrication steps can be reduced.
The protection layer may be formed in a step of forming the side wall insulation layers.
The protection layer may comprise an insulation layer formed together with the gate insulation layer, a conductive layer formed together with the gate electrode, and another insulation layer formed together with the side wall insulation layers.
The Zener diode may have a Zener voltage which is met to be lower than the avalanche breakdown voltage in the drain region. This enables to reliably cause the Zener breakdown in the Zener diode prior to the occurrence of the avalanche breakdown in the parasitic bipolar transistor. As a result, the bipolar transistor can be turned on instead of the parasitic bipolar transistor.
The Zener diode may have a Zener voltage which is set to be lower than the snapback voltage in the drain region of the MOS transistor. This causes a current to be discharged constantly through the bipolar transistor. As a result, shifting of the path of the discharging current from the bipolar transistor to the parasitic bipolar transistor can be prevented with certainty, thereby preventing electrostatic breakdown of the MOS transistor.
The fourth impurity-diffusion layer of the Zener diode may have an impurity concentration lower than the impurity concentration of the drain region. This is because the fourth impurity-diffusion layer preferably has a high resistance to prevent the current concentration at the boundary between the fourth impurity-diffusion layer and the isolation region when an electric charge is injected due to static electricity.
According to a second aspect of the present invention, there is provided a method of fabricating a semiconductor device comprising the steps of:
(a) forming a gate electrode on a first region of a first conductive type with a gate insulation layer interposed;
(b) doping the first region with impurities to form an impurity-diffusion layer of the first conductive type which is used for forming a Zener diode;
(c) forming an insulation layer on a wafer, part of the insulation layer being used for forming side wall insulation layers of the gate electrode;
(d) forming a mask layer on part of the insulation layer which corresponds to a region in which the Zener diode is formed;
(e) etching part of the insulation layer by anisotropic etching to form the sidewall insulation layers on side surfaces of the gate electrode together with a protection layer which covers the region in which the Zener diode is formed;
(f) forming impurity-diffusion layers of a second conductive type which are used to form source and drain regions; and
(g) forming silicide layers at least on the surfaces of the impurity-diffusion layers of the second conductive type which are used to form the source and drain regions.
This fabrication method has the following effects.
(1) This method can prevent problem caused by a conventional protection method which comprises the steps of forming source and drain regions, forming an oxide film over the entire surface of a wafer, and then performing the salicide process by removing the oxide film by etching only in the area for forming a silicide layer. The present method does not include the step of removing the oxide film by etching only in the area for forming a silicide layer in the salicide process, thereby preventing part of the side wall insulation layers from being removed. As a result, the breakdown voltage between the gate electrode and the source/drain regions can be sufficiently increased, thereby preventing occurrence of leakage.
(2) since the protection layer can be formed in the step of forming the side wall insulation layers and it is unnecessary to form an oxide film for masking and perform patterning in the salicide process, the number of fabrication steps can be reduced in comparison with a conventional method.
(3) It is possible to apply a full salicide process in which a silicide layer is formed on both the gate electrode and the source/drain regions.
In the step (f), another impurity-diffusion layer of the second conductive type which is electrically isolated from the drain region may be formed and used for forming an emitter region of a bipolar transistor. Since the emitter region is simultaneously formed in the step of forming the source and drain regions of the MOS transistor by providing this step, the number of fabrication steps can be reduced.
The impurity-diffusion layer of the second conductive type forming part of the Zener diode may be formed as follows. According to the following, the impurity-diffusion layer of the second conductive type to be used for forming the Zener diode can be formed in the step of forming the source and drain regions of the MOS transistor, thereby reducing the number of fabrication steps.
In the step (b), an impurity-diffusion layer of the second conductive type to be used for forming a Zener diode may be formed.
In the step (f), an impurity-diffusion layer of the second conductive type to be used for forming a Zener diode may be formed by doping the first region with impurities with the protection layer formed in the step (e) interposed.
Prior to the step (c), a predetermined area of the first region may be doped with impurities of the second conductive type having a, low concentration to form impurity-diffusion layers of the second conductive type which have low concentrations and are used for forming the source and drain regions, and also to form an impurity-diffusion layer of the second conductive type to be used for forming a Zener diode.
According to a third aspect of the present invention, there is provided a method of fabricating a semiconductor device comprising the steps of:
(a) doping a first region of a first conductive type with impurities to form an impurity-diffusion layer of the first conductive type and an impurity-diffusion layer of a second conductive type both of which are used for forming a Zener diode;
(b) forming a gate electrode on the first region with a gate insulation layer interposed;
(c) forming side wall insulation layers on side surfaces of the gate electrode;
(d) forming impurity-diffusion layers of the second conductive type to be used for forming source and drain regions, and
(e) forming silicide layers at least on the surfaces of the impurity-diffusion layers of the second conductive type to be used for forming the source and drain regions,
wherein, in the steps (b) and (c), a protection layer including an insulation layer formed together with the gate insulation layer, a conductive layer formed together with the gate electrode, and another insulation layer formed together with the side wall insulation layers is formed on a region in which the Zener diode is formed; and
wherein the impurity-diffusion layer of the second conductive type to be used for forming the Zener diode is covered with the protection layer.
This fabrication method has the same effects as the above-described first fabrication method.
In the step (d) of this fabrication method, or in the step of forming the impurity-diffusion layers of the second conductive type to be used for forming the source and drain regions, an impurity-diffusion layer of the second conductive type which is electrically isolated from the drain region may be formed and used for forming an emitter region of a bipolar transistor.